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Part1:Clock Tree Synthesis Best Practices

Astro2007-08-10 14:00:39阅读42评论0  字号：大中小 订阅

Avoiding Clock Tree Synthesis (CTS) Pitfalls. This application note discusses some common problems that many design engineers today face when they try to run CTS. It also suggests steps you can take to avoid these problems. It is always a good idea to invest the time at the beginning to understand the clock structure and the clock gating in your design.

You should also know where your gating elements are placed and the topology of your floorplan including the location of sync points. That will ensure that you are building clock trees that will give　you good timing results. This knowledge will also help you make clock tree decisions that will help CTS build better quality clock trees.

The following list provides suggestions for dealing with problems　you may encounter.

Ａ. Big insertion delays.

Some of the things you can check if you have big insertion delays are:

1. Are there delay cells in the design?

Checkto see if there are delay cells in the netlist that are present in thecurrent design. These could be causing delay that cannot be optimized and CTS is building clock trees which match all other paths to this worst insertion delay.

2. Are there cells marked "dont touch" in the design?

Therecould be cells in the design that are marked "don’t touch" whichprevents CTS from deleting them and building optimal clock trees.

3. Can the floorplan be modified to be more clock friendly?

Sometimes it helps to consider CTS (and timing) as a constraint for floorplanning. Long skinny channels leading to more long skinny placement channels will give both timing optimization and CTS problems. Consider using soft blockages or refloorplan.

4. Can you define new create_clocks that will assist CTS(divide and rule)?

Many times running CTS on the main clock pin is not　the optimal way to build clock trees.  Itmay help to divide the clock tree based on the floorplan and thesyncpins and build sub clocks, then define the sync pins and build theupper main clock.

5. Are the syncPins defined correctly for macros?

It is a good idea to check the syncPins file to see if the sync pins make sense. Also check that the numbers are accurate and that the time units are correct.

6. If there are ignore pins in the design are they defined as ignore pins?

If there are ignore pins in the design, make sure you define these as ignore pins before running CTS.

7. Have you used varRouteRules and propogated by astMarckClockTree?

Defining varRouteRules helps to reduce the insertion delay. Define shielding, and double or more width rules for clock nets, and propagate them using astMarkClockTree.

8. Are the CTU buffers marked as "dont use"?

Some technologies use clock tree buffers. Make sure you are using these only for your clock tree. Also make sure they are not marked "dont use".

9. Be creative and use different CTS intParams to get better results.

There are several CTS options in the form that you can try to change to get better or more desireable CTS results.

10. Use the Block option in CTS in the first attempt.

This usually gives better insertion and skew results. If your design is less than 5% std cell utilization try the Top option.

11. CTO is designed to work on skew and will not reduce insertion delay once it is built.

Try providing a higher skew goal during CTS.

12. Use inverters only to build the clock tree if possible.

13. Define variable route rules with greater than default widths and clearance and also shield the clock nets.

Then propagate these rules using astMarkClockTree.  This will help insertion delay.

B. Unreasonable skew.

Some of the things you can check if you have unreasonable skew are:

1. All the above except A(11).

All the issues discussed above also apply to skew debugging.

2. Do you have derived clocks that do not need skew matching?

Ifyou have clocks that get divided and some branches do not need skewbalancing with the rest, then build clock trees for them separately anddo not allow skew calculation between them. You can define sync pins or ignore pins at cross-over points.

3. Look closely at your worst path(s) for possible culprits.

Itis quite likely that some of your worst paths have an issue which ispreventing CTS from optimizing them and is causing all other paths toget delay added to match the insertion delay or better skew.

4. Use intParams areaBased and ECOWinSize to help the Overlap Removal (OV) engine.

C. CTS doesn't run properly.

Some of the things you can check if CTS doesn't run properly are:

1. All of the above.

For general quality of results issues, all the above points should be checked.

2. Are the SDC constraints loaded and is create_clock defined?

Ifthere are no create_clock statements in the SDC file loaded, CTS willnot run. Make sure you have at least one create_clock in your SDC file. It is good practice to have set_clock_transition, set_clock_latency, and set_clock_uncertainty also defined. For the SDC latency values to be honored, the intParam axSetIntParam "acts" "clock uncertainty goal" 1 should be set. CTSuses constraints in the CTS form as first priority, then it uses theconstraints in the intParams, and then it uses SDC constraints. Having these in the SDC file will also enable the timer to account for your skew and insertion delay in optimization steps.

3. If you have multiple create_clock statements in a path, did you set the "define ataPropagateClockThruCreateClock" correctly?

This is a new define parameter in the 2003.06 release and it needs to be set correctly.

4. Build the clock tree on lower clocks, then define the sync pins and run CTS on next level up (divide and conquer).

This is a good practice when building clock trees.  Always remember to define sync pins if you need them.

5. astSetDontTouch ?clock_buffers.list? #f done?

If your CTS buffers have a "dont use" property in your library, you need to set that to false.

6. Are the clock nets marked "dont touch" or is set_case_analysis defined?

Occasionally you may end up with a "dont touch" property on your clock net as a results of your analysis. Make sure you reset this using the astmarkClockTree command. Also if your SDC constraints have a set_case_analysis defined that disables the clock net, CTS will not build clock trees.

7. Is create_clock defined on a non-physical hierarchical pin?

Ifyou define create_clock on a pin that is not present physically and isonly present in the heirarchical netlist, CTS will not be able to run.

8. Try different CTS options and use the one that gives the best results.

As always, it is a good idea to experiment and try out different CTS options and intParams to get the best result.