表面磨平机:ARM Options - Using the GNU Compiler Collection (GCC)

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3.17.2 ARM Options

These `-m' options are defined for Advanced RISC Machines (ARM)architectures:

-mabi=name

Generate code for the specified ABI. Permissible values are: `apcs-gnu',`atpcs', `aapcs', `aapcs-linux' and `iwmmxt'.

-mapcs-frame

Generate a stack frame that is compliant with the ARM Procedure CallStandard for all functions, even if this is not strictly necessary forcorrect execution of the code. Specifying -fomit-frame-pointerwith this option will cause the stack frames not to be generated forleaf functions. The default is -mno-apcs-frame.

-mapcs

This is a synonym for -mapcs-frame.

-mthumb-interwork

Generate code which supports calling between the ARM and Thumbinstruction sets. Without this option the two instruction sets cannotbe reliably used inside one program. The default is-mno-thumb-interwork, since slightly larger code is generatedwhen -mthumb-interwork is specified.

-mno-sched-prolog

Prevent the reordering of instructions in the function prolog, or themerging of those instruction with the instructions in the function'sbody. This means that all functions will start with a recognizable setof instructions (or in fact one of a choice from a small set ofdifferent function prologues), and this information can be used tolocate the start if functions inside an executable piece of code. Thedefault is -msched-prolog.

-mfloat-abi=name

Specifies which floating-point ABI to use. Permissible valuesare: `soft', `softfp' and `hard'.

Specifying `soft' causes GCC to generate output containinglibrary calls for floating-point operations.`softfp' allows the generation of code using hardware floating-pointinstructions, but still uses the soft-float calling conventions.`hard' allows generation of floating-point instructionsand uses FPU-specific calling conventions.

The default depends on the specific target configuration. Note thatthe hard-float and soft-float ABIs are not link-compatible; you mustcompile your entire program with the same ABI, and link with acompatible set of libraries.

-mhard-float

Equivalent to -mfloat-abi=hard.

-msoft-float

Equivalent to -mfloat-abi=soft.

-mlittle-endian

Generate code for a processor running in little-endian mode. This isthe default for all standard configurations.

-mbig-endian

Generate code for a processor running in big-endian mode; the default isto compile code for a little-endian processor.

-mwords-little-endian

This option only applies when generating code for big-endian processors.Generate code for a little-endian word order but a big-endian byteorder. That is, a byte order of the form `32107654'. Note: thisoption should only be used if you require compatibility with code forbig-endian ARM processors generated by versions of the compiler prior to2.8.

-mcpu=name

This specifies the name of the target ARM processor. GCC uses this nameto determine what kind of instructions it can emit when generatingassembly code. Permissible names are: `arm2', `arm250',`arm3', `arm6', `arm60', `arm600', `arm610',`arm620', `arm7', `arm7m', `arm7d', `arm7dm',`arm7di', `arm7dmi', `arm70', `arm700',`arm700i', `arm710', `arm710c', `arm7100',`arm720',`arm7500', `arm7500fe', `arm7tdmi', `arm7tdmi-s',`arm710t', `arm720t', `arm740t',`strongarm', `strongarm110', `strongarm1100',`strongarm1110',`arm8', `arm810', `arm9', `arm9e', `arm920',`arm920t', `arm922t', `arm946e-s', `arm966e-s',`arm968e-s', `arm926ej-s', `arm940t', `arm9tdmi',`arm10tdmi', `arm1020t', `arm1026ej-s',`arm10e', `arm1020e', `arm1022e',`arm1136j-s', `arm1136jf-s', `mpcore', `mpcorenovfp',`arm1156t2-s', `arm1156t2f-s', `arm1176jz-s', `arm1176jzf-s',`cortex-a5', `cortex-a8', `cortex-a9', `cortex-a15',`cortex-r4', `cortex-r4f', `cortex-m4', `cortex-m3',`cortex-m1',`cortex-m0',`xscale', `iwmmxt', `iwmmxt2', `ep9312'.

-mtune=name

This option is very similar to the -mcpu= option, except thatinstead of specifying the actual target processor type, and hencerestricting which instructions can be used, it specifies that GCC shouldtune the performance of the code as if the target were of the typespecified in this option, but still choosing the instructions that itwill generate based on the CPU specified by a -mcpu= option.For some ARM implementations better performance can be obtained by usingthis option.

-march=name

This specifies the name of the target ARM architecture. GCC uses thisname to determine what kind of instructions it can emit when generatingassembly code. This option can be used in conjunction with or insteadof the -mcpu= option. Permissible names are: `armv2',`armv2a', `armv3', `armv3m', `armv4', `armv4t',`armv5', `armv5t', `armv5e', `armv5te',`armv6', `armv6j',`armv6t2', `armv6z', `armv6zk', `armv6-m',`armv7', `armv7-a', `armv7-r', `armv7-m',`iwmmxt', `iwmmxt2', `ep9312'.

-mfpu=name

-mfpe=number

-mfp=number

This specifies what floating point hardware (or hardware emulation) isavailable on the target. Permissible names are: `fpa', `fpe2',`fpe3', `maverick', `vfp', `vfpv3', `vfpv3-fp16',`vfpv3-d16', `vfpv3-d16-fp16', `vfpv3xd', `vfpv3xd-fp16',`neon', `neon-fp16', `vfpv4', `vfpv4-d16',`fpv4-sp-d16' and `neon-vfpv4'.-mfp and -mfpe are synonyms for-mfpu=`fpe'number, for compatibility with older versionsof GCC.

If -msoft-float is specified this specifies the format offloating point values.

If the selected floating-point hardware includes the NEON extension(e.g. -mfpu=`neon'), note that floating-pointoperations will not be used by GCC's auto-vectorization pass unless-funsafe-math-optimizations is also specified. This isbecause NEON hardware does not fully implement the IEEE 754 standard forfloating-point arithmetic (in particular denormal values are treated aszero), so the use of NEON instructions may lead to a loss of precision.

-mfp16-format=name

Specify the format of the __fp16 half-precision floating-point type.Permissible names are `none', `ieee', and `alternative';the default is `none', in which case the __fp16 type is notdefined. See Half-Precision, for more information.

-mstructure-size-boundary=n

The size of all structures and unions will be rounded up to a multipleof the number of bits set by this option. Permissible values are 8, 32and 64. The default value varies for different toolchains. For the COFFtargeted toolchain the default value is 8. A value of 64 is only allowedif the underlying ABI supports it.

Specifying the larger number can produce faster, more efficient code, butcan also increase the size of the program. Different values are potentiallyincompatible. Code compiled with one value cannot necessarily expect towork with code or libraries compiled with another value, if they exchangeinformation using structures or unions.

-mabort-on-noreturn

Generate a call to the function abort at the end of anoreturn function. It will be executed if the function tries toreturn.

-mlong-calls

-mno-long-calls

Tells the compiler to perform function calls by first loading theaddress of the function into a register and then performing a subroutinecall on this register. This switch is needed if the target functionwill lie outside of the 64 megabyte addressing range of the offset basedversion of subroutine call instruction.

Even if this switch is enabled, not all function calls will be turnedinto long calls. The heuristic is that static functions, functionswhich have the `short-call' attribute, functions that are insidethe scope of a `#pragma no_long_calls' directive and functions whosedefinitions have already been compiled within the current compilationunit, will not be turned into long calls. The exception to this rule isthat weak function definitions, functions with the `long-call'attribute or the `section' attribute, and functions that are withinthe scope of a `#pragma long_calls' directive, will always beturned into long calls.

This feature is not enabled by default. Specifying-mno-long-calls will restore the default behavior, as willplacing the function calls within the scope of a `#pragmalong_calls_off' directive. Note these switches have no effect on howthe compiler generates code to handle function calls via functionpointers.

-msingle-pic-base

Treat the register used for PIC addressing as read-only, rather thanloading it in the prologue for each function. The run-time system isresponsible for initializing this register with an appropriate valuebefore execution begins.

-mpic-register=reg

Specify the register to be used for PIC addressing. The default is R10unless stack-checking is enabled, when R9 is used.

-mcirrus-fix-invalid-insns

Insert NOPs into the instruction stream to in order to work aroundproblems with invalid Maverick instruction combinations. This optionis only valid if the -mcpu=ep9312 option has been used toenable generation of instructions for the Cirrus Maverick floatingpoint co-processor. This option is not enabled by default, since theproblem is only present in older Maverick implementations. The defaultcan be re-enabled by use of the -mno-cirrus-fix-invalid-insnsswitch.

-mpoke-function-name

Write the name of each function into the text section, directlypreceding the function prologue. The generated code is similar to this:

               t0
                   .ascii "arm_poke_function_name", 0
                   .align
               t1
                   .word 0xff000000 + (t1 - t0)
               arm_poke_function_name
                   mov     ip, sp
                   stmfd   sp!, {fp, ip, lr, pc}
                   sub     fp, ip, #4
     

When performing a stack backtrace, code can inspect the value ofpc stored at fp + 0. If the trace function then looks atlocation pc - 12 and the top 8 bits are set, then we know thatthere is a function name embedded immediately preceding this locationand has length ((pc[-3]) & 0xff000000).

-mthumb

Generate code for the Thumb instruction set. The default is touse the 32-bit ARM instruction set.This option automatically enables either 16-bit Thumb-1 ormixed 16/32-bit Thumb-2 instructions based on the -mcpu=nameand -march=name options. This option is not passed to theassembler. If you want to force assembler files to be interpreted as Thumb code,either add a `.thumb' directive to the source or pass the -mthumboption directly to the assembler by prefixing it with -Wa.

-mtpcs-frame

Generate a stack frame that is compliant with the Thumb Procedure CallStandard for all non-leaf functions. (A leaf function is one that doesnot call any other functions.) The default is -mno-tpcs-frame.

-mtpcs-leaf-frame

Generate a stack frame that is compliant with the Thumb Procedure CallStandard for all leaf functions. (A leaf function is one that doesnot call any other functions.) The default is -mno-apcs-leaf-frame.

-mcallee-super-interworking

Gives all externally visible functions in the file being compiled an ARMinstruction set header which switches to Thumb mode before executing therest of the function. This allows these functions to be called fromnon-interworking code. This option is not valid in AAPCS configurationsbecause interworking is enabled by default.

-mcaller-super-interworking

Allows calls via function pointers (including virtual functions) toexecute correctly regardless of whether the target code has beencompiled for interworking or not. There is a small overhead in the costof executing a function pointer if this option is enabled. This optionis not valid in AAPCS configurations because interworking is enabledby default.

-mtp=name

Specify the access model for the thread local storage pointer. The validmodels are soft, which generates calls to __aeabi_read_tp,cp15, which fetches the thread pointer from cp15 directly(supported in the arm6k architecture), and auto, which uses thebest available method for the selected processor. The default setting isauto.

-mword-relocations

Only generate absolute relocations on word sized values (i.e. R_ARM_ABS32).This is enabled by default on targets (uClinux, SymbianOS) where the runtimeloader imposes this restriction, and when -fpic or -fPICis specified.

-mfix-cortex-m3-ldrd

Some Cortex-M3 cores can cause data corruption when ldrd instructionswith overlapping destination and base registers are used. This option avoidsgenerating these instructions. This option is enabled by default when-mcpu=cortex-m3 is specified.